1. Field of the Invention
The present invention relates to a data transmission line used continuously connected in a plurality of stages in an asynchronous system. More specifically, the present invention relates to a data transmission line used continuously connected in a plurality of stages in an asynchronous system which is capable of taking data from external dock synchronous system and allows transmission.
2. Description of the Background Art
A data transmission apparatus employing asynchronous hand shake method is sometimes used for data input/output operation using FIFO (First In First Out) memory or data processing apparatus including data driven type information processing operation. In such a data transmission apparatus, a plurality of data transmission lines are connected, and autonomous data transfer takes place with each of the data transmission lines transmitting/receiving to and from each other a data transmission request and a transfer acknowledge (Acknowledge) signal indicating whether data transfer is acknowledged or not.
FIG. 7 is a block diagram showing an example of a conventional data transmission apparatus adapting handshake method.
FIG. 8 is a block diagram showing a configuration of the data transmission line shown in FIG. 7.
Referring to FIG. 7, the data transmission apparatus includes data transmission lines 10, 20 and 30. The data transmission lines include transfer control circuits 10A, 20A and 30A as well as data holding circuits 10B, 20B and 30B, respectively. Each data transmission line is connected to a sequence through a prescribed logic circuit. FIG. 7 shows a configuration where data is sequentially processed by logic circuits 15→25→35 while the data is transferred through data transmission lines 10→20→30, in this order.
FIG. 8 shows block configuration of each data transmission line shown in FIG. 7. In FIG. 8, block configuration of data transmission line 10 is shown as a representative. Other data transmission lines have similar configuration, and therefore description thereof is not repeated. Referring to FIG. 8, data transmission line 10 includes a self-synchronous type transfer control circuit 10A and a data holding circuit 10B formed of a D type flip-flop.
Transfer control circuit 10a receives as an input a pulse CI from a preceding stage (not shown), outputs acknowledge signal RO indicating acknowledgement or inhibition of transfer to the preceding stage, outputs a pulse CO to a succeeding stage (not shown), receives as an input an acknowledge signal RI representing acknowledgement or inhibition of data transfer from the succeeding stage, and outputs a clock pulse CP controlling data holding operation to data holding circuit 10B.
Upon reception of pulse CI from the preceding stage, when acknowledge signal RI from the succeeding stage indicates acknowledged state, transfer control circuit 10A outputs pulse CO to the succeeding stage, and outputs pulse CP to data holding circuit 10B. In response to pulse CP applied from transfer control circuit 10A, data holding circuit 10B holds data DI applied from the preceding stage, and outputs the held data as data DO to the succeeding stage.
The data transmission line of FIG. 7 will be described with reference to FIG. 8. Referring to FIG. 7, transfer request signal C20 is transmitted as pulses CI and CO from transfer control circuit 10A to 20A. A transfer request signal C30 as pulses CO and CI is transmitted from transfer control circuit 20A to transfer control circuit 30A. Acknowledge signal R20 is transmitted as acknowledge signals RO and RI from transfer control circuit 20A to transfer control circuit 10A. Acknowledge signal R30 as acknowledge signals RO and RI is transmitted from transfer control circuit 30A to 20A. Transfer control circuit 10A receives transfer request signal C10, as pulse CI, from a transfer control circuit of a preceding stage, not shown. A transfer request signal C40 is output as pulse CO to a transfer control circuit of a succeeding stage, not shown, from transfer control circuit 30A. Acknowledge signal RIO is output as acknowledge signal RO from transfer control circuit 10A to a transfer control circuit of a preceding stage, not shown. Transfer control circuit 30A receives acknowledge signal R40 as acknowledge signal RI, from a transfer control circuit of a succeeding stage, not shown.
Referring to FIG. 7, when data transmission line 10 is at a data holding state and data transmission line 20 of the succeeding stage is at a data holding state, data is not transmitted from data transmission line 10 to data transmission line 20. When data transmission line 20 of the succeeding stage is in a state not holding data (or when it attains the state not holding data), data is transmitted from data transmission line 10 to data transmission line 20 with at least a preset delay time.
The above described manner of control where data is transferred asynchronously in accordance with transfer request signals and acknowledge signals transmitted/received to and from adjacent data transmission lines with at least a preset delay time is referred to as self-synchronous transfer control, and a circuit controlling such data transfer is referred to as self-synchronous transfer control circuit.
FIG. 9 is a circuit diagram showing an example of a conventional self-synchronous transfer control circuit. FIG. 10 is a time chart related to the operation of the circuit shown in FIG. 9.
The circuit of FIG. 9 receives pulse CI as the transfer request signal from a preceding stage, not shown, and outputs acknowledge signal RO to the preceding stage, not shown. Further, the circuit outputs pulse CO as the transfer request signal to a succeeding stage, not shown, and receives acknowledge signal RI from the succeeding stage, not shown. Further, the circuit of FIG. 9 receives a master reset signal /MR (/MR represents an inversion of MR).
In the following, “H” and “L” represent High and Low signal levels, respectively.
The circuit of FIG. 9 includes RS flipflops 111 and 112, inverters 130, 170 and 180, a 4-input NAND gate 140 and a delay element 190. RS flipflop 111 includes NAND gates 110 and 120, and when a pulse of “L” level is applied to a node /S, RS flipflop 111 is set in response. Thus RS flipflop 111 stores “L” pulse, and provides a signal at “H” level at a node Q. When “L” pulse is applied to a node /R, RS flipflop 111 is reset. Thus, RS flipflop 111 outputs a signal of “L” at node Q. RS flipflop 112 includes NAND gates 150 and 160. The operation of RS flipflop 112 is similar to that of RS flipflop 111.
Pulse CI is applied to a first input, an output signal from node Q of RS flipflop 111 is applied to a second input, acknowledge signal RI is applied to a third input and an output signal from inverter 180 is applied to a fourth input, of 4-input NAND gate 140.
That the acknowledge signal RO is at “H” means that the circuit of FIG. 9 acknowledges transfer of data from the proceeding stage, and that the signal is at “L” means that data transfer from the preceding stage is inhibited. That the pulse CI is at “L” represents that a data transfer is requested from the preceding stage and that the pulse CI is at “H” means that data transfer is not requested from the preceding stage.
The operation of the transfer control circuit shown in FIG. 9 will be described with reference to the time chart of FIG. 10.
In FIG. 10, the ordinate represents signal levels of various signals shown in FIG. 9, and the abscissa represents time.
First, when a pulse at “L” is applied as master reset signal /MR, the transfer control circuit of FIG. 9 is initialized. Consequently, pulse CO, the output at node /Q and acknowledge signal RO attain “H”, respectively.
When acknowledge signal RO indicates acknowledged state in the circuit of FIG. 9 and the pulse CI is applied at “L” from the preceding stage at time T of FIG. 10, RS flipflop 111 is set, and the output of node Q attains “H”. Consequently, acknowledge signal RO attains “L” (inhibited state), whereby further data transfer from the preceding stage is inhibited. After a prescribed time period, the pulse CI attains “H”. The output G from NAND gate 140 attains “L” when RS flipflop 111 stores reception of a data transfer request from the preceding stage of the circuit shown in FIG. 9 (that is, output of node Q is at “H”), pulse CI is returned to “H”, the transfer control circuit is not issuing data transfer request to the succeeding stage (that is, pulse CO is at “H”) and acknowledge signal RI indicates acknowledged state (signal RI is at “H”). When the output G from NAND gate 140 attains “L”, RS flipflop 111 is reset, and RS flipflop 112 is also reset. As the output of RS flipflop 112 is at “L”, the pulse CP applied to the corresponding data holding circuit obtained through inverter 170 rises to “H”. A clock pulse for holding data is applied to the corresponding data holding circuit when pulse CP rises to “H” and, in response, the data holding circuit latches applied data DI and outputs this as data DO. Further, the output of inverter 170 passes through inverter 180 and delay element 190, and sets the pulse CO to “L”. Consequently, the pulse CI to be applied to the transfer control circuit of the succeeding stage is set to “L”, so as to request data transfer to the transfer control circuit of the succeeding stage. Accordingly, the transfer control circuit of the succeeding stage receives the transfer request signal from the transfer control circuit in the preceding stage.
After the lapse of a prescribed time period, the circuit of FIG. 9 receives acknowledge signal RI set at the inhibited state (“L”) from the transfer control circuit of the succeeding stage which has received the transfer request signal, and hence flipflop 112 is set. Accordingly, clock pulse CP attains “L” and the pulse CO returns to “H”.
Thereafter, the data transmission line of the succeeding stage transfers data to the data transmission line of the second succeeding stage, whereby the acknowledge signal RI in the circuit shown in FIG. 9 returns to “H”. This allows new data transfer to the data transmission line of the succeeding stage.
An improvement of the transfer control circuit described above is proposed in Japanese Patent Laying-Open No. 6-83731. Here, the content, which is described in detail in this laid-open application, will be briefly outlined. According to the disclosure of the laid-open application, a self-synchronous transfer control circuit is provided which can acknowledge or prohibit data transfer at an arbitrary timing. Therefore, in data transfer lines and logic circuits arranged between the data transfer lines, formed incorporating the self-synchronous transfer control circuit provided in accordance with the disclosure of the laid-open application, it is possible to perform, step by step, timing verification of data or signal transfer and tracing of operation in debugging the processed contents.
In the above described conventional transfer control circuit, when the data transmission line of the succeeding stage is in an empty state (acknowledge signal RI is “H”), data is autonomously and successively transferred to the data transmission lines of the succeeding stages. Assuming that data output from an external dock synchronized circuit such as a clock or a register in which result of calculation by a CPU (Central Processing Unit) is written is taken into the asynchronous data transmission line in the middle of the data transfer apparatus, the output data of the clock synchronous circuit will be taken into the data holding circuit at a timing, represented by the signal level of clock pulse CP from the transfer control circuit.
The clock driving the clock synchronous circuit is not at all co-related to the clock pulse CP output from the transfer control circuit in the asynchronous data transmission line, in other words, the asynchronous system operates at an arbitrary timing independent from the synchronous system, the data output from the clock synchronous circuit is taken into the data holding circuit at a timing which cannot be expected at all. Therefore, the data output from the clock synchronous circuit cannot taken in the data holding circuit at desired timing and, further, it is possible that the data which is in transition in the clock synchronous circuit may undesirably be taken in the data holding circuit.
The technique disclosed in Japanese Patent Laying-Open No. 6-83731 mentioned above is directed to debugging of a data processing apparatus including a data driven type information processing unit. It is not directed to debugging of an IC on which data driven type information processing unit and a clock synchronous circuit such as a von Neumann type CPU mounted mixedly. Therefore, the technique does not take into consideration taking of data output from an external clock synchronous circuit to an asynchronous data transmission line in the middle of the data transfer apparatus. Therefore, it has been impossible to take in data (signal) output from an external synchronous system in a data transmission line of an asynchronous system including data driven type information processing unit, at a desired arbitrary timing.